This invention relates to improvement of a signal electrode drive apparatus which is contained in the display-drive circuit for use in a liquid crystal display device.
A portable television employs a liquid crystal display device to provide its picture. An example of this known type of TV set is disclosed in U.S. Pat. No. 4,581,654. The display-drive circuit of this prior art TV set is configured as shown in FIGS. 1 through 3. FIG. 1 shows a configuration of the overall display-drive circuit. In the figure, reference numeral 1 designates a simple matrix liquid crystal display panel of, for example, 120.times.160 dots. Numeral 2 designates a scanning electrode drive circuit, and 3a and 3b denotes signal electrode drive circuits. Scanning electrode drive circuit 2 sequentially drives scanning electrodes X1 to X120 of display panel 1. The sequential drive operation is timed by a timing signal from a controller (not shown). Signal electrode drive circuits 3a and 3b drive groups of signal electrodes Y1 to Y80 and Y81 to Y160, respectively. The drive operation is performed using an n-bit digital signal, passed through an A/D converter, and a timing signal from the controller. More specifically, circuit 3a fetches the data of 80 lines, which comprise the left-hand portion of the input data record during the effective horizontal scanning period. Electrode drive circuit 3b fetches the data of 80 lines in the right-hand portion. On the basis of the fetched data, drive circuits 3a and 3b drive the respective groups of electrodes Y1 to Y80 and Y81 to Y160, in synchronism with the driving of scanning electrodes Xl to X120.
FIG. 2 shows in block diagraph the details of the prior art signal electrode drive circuit 3a. In the figure, shift register 11 is provided in each stage of 80 stages, and which consists of a 4-bit register. The 4-bit video data coming from an A/D converter (not shown) is sequentially stored in the the shift register, in synchronization with sampling clock .phi.s. The data loaded is transferred to graduation signal-forming circuit 13, via buffer 12 which consists of 80 stages, each stage including 4-bit buffer registers, and which operates in synchronism with a latch pulse .phi..
Intensity modulation pulse-generating circuit 15 responds to latch pulse .phi.L and counts clock pulse .phi.2, to form intensity modulation pulses P1 to P4. These pulses Pl to P4 are input to graduation signal-forming circuit 13. Circuit 15 contains a counter, which is reset by latch pulse .phi.L, and which frequency-divides, by 2, the frequency of clock pulse .phi.2, to form intensity modulation pulses P1 to P4. Clock pulse .phi.2 is a fundamental clock signal with a frequency of 3 MHz. Graduation signal-forming circuit 13 appropriately processes the 4-bit video data latched in buffer 12, and the intensity modulation pulses P1 to P4 generated by intensity modulation pulse-generating circuit 15, and forms 16 types of graduation signals S1 to S80 with different time widths. These graduation signals are transferred to 2-channel analog multiplexer 14. Multiplexer 14 also appropriately processes graduation signals S1 to S80 from graduation signal-forming circuit 13 and field-select signal .phi.f, and forms signal electrode drive signals Y1 to Y80, to drive liquid crystal display panel 1.
FIG. 3 shows in detail one stage of the signal electrode drive circuit of FIG. 2 which consists of 80 stages, as previously stated. As is shown in shift register 11, each stage is made up of one register 111 of 4 bits, which is operated in response to sampling clock pulse .phi.s. Data of 4 bits D1 to D4 coming from the A/D converter (not shown) are loaded into register 111, and then transferred to register 112, at the next stage. Buffer 12 includes a 4-bit buffer register 121 in each stage of 80 stages. The data from register 111 is loaded into buffer register 121 in synchronism with latch pulse .phi.L. The data is then transferred to graduation signal-forming circuit 13. Graduation signal-forming circuit 13 consists of OR circuits 131 to 134, AND circuit 135, and flip-flop 136 to 138. The data from buffer register 121, together with intensity-modulation pulses P1 to P4 from modulation pulse-generating circuit 25, is input to AND circuit 135, via OR circuits 131 to 134. The output data from AND circuit 135 is input to flip-flop 136, in synchronism with clock pulse .phi.2. The output data of flip-flop 136 is input to the reset terminal R of flip-flop 137. Flip-flop 137 is set by latch pulse .phi.L. Flip-flop 136 is reset by latch pulse .phi.L. The output signal of flip-flop 137 is loaded into flip-flop 138, in synchronism with clock pulse .phi.2. The output signal from flip-flop 138 is transferred, as a graduation signal Si, to analog multiplexer 14. Multiplexer 14 is made up of decoder 141, and transfer gates 142 to 145. Multiplexer 14 receives a graduation signal Si and a frame-select signal .phi.f. Transfer gates 142 to 145 are coupled with V5, V2, V3, and V0, respectively. These gates are gate-controlled by the output signal from decoder 141. By way of this gate control, one of voltages V5, V2, V3, and V0 is selected and output as a signal electrode drive signal Yi.
As can be seen from the foregoing, the signal electrode drive circuit is arranged such that each stage of shift register 11 is made up of a register 111. Shift register 11 in each stage of 80 stages contains register 111, 112, . . . , respectively, each of which transfers the video data of 4-bits. Register 111 is comprised of, for example, inverter including two transistors, and a clocked inverter including four transistors. The fact that the signal electrode drive circuit requires 80 stages for transferring video data at high speed, for example, 3 MHz which is the frequency of the fundamental clock signal, implies an increase in current dissipation in that drive circuit.